| 0x1 | Initialization of the High Precision Event Timer failed due to a BIOS configuration problem.%nThe operating system will use another available platform timer in lieu of the High Precision Event Timer.%n%nContact your system vendor for technical assistance.%nInitialization status: %1. |
Initialization of the High Precision Event Timer failed due to a BIOS configuration problem.%nThe operating system will use another available platform timer in lieu of the High Precision Event Timer.%n%nContact your system vendor for technical assistance.%nInitialization status: %1. |
| 0x2 | Initialization of the High Precision Event Timer failed due to unsupported hardware.%nThe operating system will use another available platform timer in lieu of the High Precision Event Timer.%n%nInitialization status: %1. |
Initialization of the High Precision Event Timer failed due to unsupported hardware.%nThe operating system will use another available platform timer in lieu of the High Precision Event Timer.%n%nInitialization status: %1. |
| 0x3 | Initialization of the High Precision Event Timer failed due to an interrupt configuration problem.%nThe operating system will use another available platform timer in lieu of the High Precision Event Timer.%n%nIt may be possible to address this problem with an updated system BIOS.%nContact your system vendor for technical assistance.%nInitialization status: %1. |
Initialization of the High Precision Event Timer failed due to an interrupt configuration problem.%nThe operating system will use another available platform timer in lieu of the High Precision Event Timer.%n%nIt may be possible to address this problem with an updated system BIOS.%nContact your system vendor for technical assistance.%nInitialization status: %1. |
| 0x4 | Due to an unexpected condition, the operating system will use another available platform timer in lieu of the processor's cycle counters. Status: %1. |
Due to an unexpected condition, the operating system will use another available platform timer in lieu of the processor's cycle counters. Status: %1. |
| 0xB | The High Precision Event Timer failed to deliver message signalled interrupts. The operating system will fall back to line based interrupts for this timer.%nInitialization status: %1. |
The High Precision Event Timer failed to deliver message signalled interrupts. The operating system will fall back to line based interrupts for this timer.%nInitialization status: %1. |
| 0xC | The platform firmware has corrupted memory across the previous system power transition. Please check for updated firmware for your system. |
The platform firmware has corrupted memory across the previous system power transition. Please check for updated firmware for your system. |
| 0xD | The system watchdog timer was triggered. |
The system watchdog timer was triggered. |
| 0x50000002 | Error |
Error |
| 0x50000003 | Warning |
Warning |
| 0x50000004 | Information |
Information |
| 0x50000005 | Verbose |
Verbose |
| 0x90000001 | Microsoft-Windows-HAL |
Microsoft-Windows-HAL |
| 0x90000002 | System |
System |
| 0x90000003 | Microsoft-Windows-HAL/Debug |
Microsoft-Windows-HAL/Debug |
| 0xB0000005 | Due to an expected condition, the operating system will use another available platform timer in lieu of the processor's cycle counters. Status: %1. |
Due to an expected condition, the operating system will use another available platform timer in lieu of the processor's cycle counters. Status: %1. |
| 0xB0000007 | The processor cycle counter on processor %2 has been probed by processor %1. A counter delta of %3 was detected. The approximate communication delay between these processors was detected to be %4. |
The processor cycle counter on processor %2 has been probed by processor %1. A counter delta of %3 was detected. The approximate communication delay between these processors was detected to be %4. |
| 0xB0000008 | The processor's cycle counters have been successfully synchronized from processor %1 within acceptable operating thresholds. The maximum positive delta detected was %3 and the maximum negative delta was %4. Synchronization executed for %5 microseconds. |
The processor's cycle counters have been successfully synchronized from processor %1 within acceptable operating thresholds. The maximum positive delta detected was %3 and the maximum negative delta was %4. Synchronization executed for %5 microseconds. |
| 0xB0000009 | The processor cycle counter on processor %2 was synchronized against processor %1 using an adjustment of %4 cycles on attempt %5. This resulted in a delta of %3 cycles. |
The processor cycle counter on processor %2 was synchronized against processor %1 using an adjustment of %4 cycles on attempt %5. This resulted in a delta of %3 cycles. |
| 0xB000000A | The synchronization of the processor's cycle counters was not able to synchronize the processors within acceptable operating thresholds. Status: %1. |
The synchronization of the processor's cycle counters was not able to synchronize the processors within acceptable operating thresholds. Status: %1. |
| 0xB000000E | The watchdog wake timer was triggered. |
The watchdog wake timer was triggered. |